Anti-fuse structure for reducing contamination of the anti-fuse material

ABSTRACT

An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

.Iadd.This application is a reissue of application Ser. No. 08/275,187,filed Jul. 14, 1994, now U.S. Pat. No. 5,493,146. .Iaddend.

BACKGROUND OF THE INVENTION

This invention relates generally to integrated circuits and, morespecifically, to anti-fuse structures in integrated circuits.

Programmable integrated circuits include such devices asfield-programmable gate arrays and programmable read-only memories(PROMS). Such devices may include elements such as fuses or anti-fusesto enable them to be programmed.

Field programmable gate arrays include a large number of logic elements,such as AND gates and OR gates, which can be selectively coupledtogether by devices like fuses or anti-fuses to perform user-designedfunctions. The several types of PROMS, including standard, write-oncePROMS, erasable programmable read-only memories (EPROMS), electricallyerasable programmable read-only memories (EEPROMS), etc., usuallycomprise an array of memory cells arranged in rows and columns which canbe programmed to store user data. An unprogrammed anti-fuse gate arrayor PROM is programmed by causing selected anti-fuses to becomeconductive.

Anti-fuses include a material which initially has a high resistance butwhich can be converted into a low resistance material by the applicationof a programming voltage. For example, amorphous silicon (A-Si), whichhas an intrinsic resistivity of approximately 1 megohm-cm, can befashioned into 1 micron wide vias having a resistance of approximately1-2 gigohms. These vias can then be transformed into a low resistancestate by the application of a voltage in the range of 10-12 volts d.c.to form vias having a resistance less than 200 ohms. These lowresistance vias can couple together logic elements of a fieldprogrammable gate array so that the gate array will perform user-definedfunctions or connect large functional blocks, or can serve as memorycells of a PROM.

An anti-fuse device is typically formed on a semiconductor wafer bydepositing a bottom electrode layer, such as titanium-tungsten (TiW),depositing an oxide layer over the electrode layer, forming a viathrough the oxide layer to the electrode layer, and depositing A-Si intothe via. A second layer of TiW can be deposited over the A-Si with analuminum (Al) layer deposited over the TiW layer.

Problems arise in the above-described structure by "cusping" or thinningof the A-Si at the corners of the via that can lead to leakage andprogramming problems. Further, cusps formed in the A-Si layer can leadto poor step coverage of the TiW layer over the A-Si. This can cause aninadequate TiW barrier to be formed separating the top Al layer from theA-Si, which can compromise the reliability of the anti-fuse, because Alis known to degrade or "poison" an anti-fuse structure by diffusing intothe A-Si layer.

A prior art solution to this problem provides oxide spacers over thecusps of the A-Si. Such a structure is described in U.S. Pat. No.5,120,679 issued to Boardman et al., the disclosure of which isincorporated herein by reference. This spacer better protects thecorners of the via where the cusping or thinning of the A-Si isproblematic. The spacer also improves the topography for the subsequentTiW barrier layer deposition. The use of dielectric spacers reducesleakage current and enhances reliability. However, the use of spacersmay increase production time and cost. Further, the use of spacersresults in reduced scalability of the structure below 1.0 micron (μm).

Alternatively, another anti-fuse structure is used for technology scaledto 0.8 μm, as the cross-sectional view of the anti-fuse structure inFIG. 1 illustrates. Overlying a silicon wafer substrate 8 on which abase oxide layer 9 has been formed are a first metal layer 10 (typicallyAl) and an inter-metal oxide (IMO) layer 12. A layer 14 of TiW isdeposited and patterned to form a conductive "strap". Followingformation of layer 14, a layer of A-Si 16 is deposited and thenpatterned to remain only in the desired locations overlying the TiWpatterned layer 14. Thus, the A-Si is not deposited in the via as in theprior anti-fuse structures, but rather, forms a separate, planar layer.An oxide layer 18 is then deposited, followed by the etching of a via 20through the oxide layer 18 to the A-Si layer 16. A barrier layer 22 ofTiW is then preferably deposited over the oxide and into the via 20 tocontact the A-Si layer 16. Subsequently, metal layer 24, preferably Al,is then deposited over the TiW layer, which prevents the Al layer 24from poisoning the A-Si layer 16.

While the above-described structure is usable with 0.8 μm anti-fusetechnology, the integrity of the anti-fuse is dependent on the integrityof the TiW barrier layer 22. This barrier layer has a problem of cuspingor thinning at the corners 21 of the via 20. This cusping makes thecorners more permeable to the migration of Al atoms from layer 24, whichcan lead to Al layer 24 diffusing into the A-Si layer 16, thereby"poisoning" the A-Si layer 16 at that point. By "poisoning" it is meantthat the conductive aluminum atoms in the A-Si layer change theconductivity of the layer such that it cannot be properly programmed orread. The problem increases as the via is scaled to widths below 0.8 μm.

What is needed is an anti-fuse structure that retains the simplicity ofthe planar A-Si approach as illustrated in FIG. 1, but which does nothave the problems associated with this approach, especially as the viawidth is scaled below 0.8 μm.

SUMMARY OF THE INVENTION

In accordance with the present invention, an anti-fuse structure andmethod for forming an anti-fuse structure are described. In general, theanti-fuse structure uses a planar anti-fuse layer and is scalable tosub-micron size. Further, the problem of Al migration into the anti-fuselayer is overcome by the use of a non-Al conductor as a plug within thevia hole.

A method for making an anti-fuse structure begins with the formation ofa conductive base layer. An anti-fuse layer is then formed over theconductive base layer. Following this, an insulating layer is formedover the anti-fuse layer. A via hole is then etched through theinsulating layer to the anti-fuse layer with the lateral dimension ofthe via being no more than approximately 0.8 microns. A conductivebarrier material is then used to form a layer over the insulating layerand in the via hole to contact the anti-fuse layer. The conductivebarrier material preferably consists essentially of TiW or TiN. A Wlayer is deposited after the conductive barrier material layer isformed. This W layer is preferably formed as a blanket layer, which isthen etched-back to form a W plug in the via hole. An Al layer ispreferably formed over the conductive barrier material and the W plug toact as the top conductive layer. The completed anti-fuse structure isthen programmable by applying a programming voltage between theconductive base layer and the conductive barrier material, and isreadable by application of a lower, sensing voltage between the layers,as is conventional in the art.

An anti-fuse structure in accordance with the present invention includesa conductive layer base. A layer of anti-fuse material overlies theconductive base layer. On top of the anti-fuse layer is an insulatinglayer, in which a via hole is formed to the anti-fuse layer. The lateraldimension of the via hole is preferably less than about 0.8 microns.Provided in the via hole to contact the anti-fuse material and over theinsulating layer is a conductive barrier material preferably includingeither TiN or TiW. The structure also includes a W plug. This plug isformed by blanket deposition over the conductive barrier material, whichis subsequently etched-back by well known processes. A top layer of Alis further included in the structure over the conductive barriermaterial. The structure is then programmable by application of aprogramming voltage and readable by application of a sensing voltage,which is lower than the programming voltage.

An advantage of the anti-fuse formed by the present invention is thatthere is no aluminum in the via hole to potentially poison the amorphoussilicon. Further, the material and process used to form the non-aluminumvias are standard, so that the process and structure of the presentinvention are quite compatible with and easily incorporated intoconventional semiconductor manufacturing processes.

These and other advantages of the present invention will become apparentupon reading the following detailed descriptions and studying thevarious figures of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an anti-fuse structure of the priorart;

FIGS. 2-5 illustrate a step-by-step cross-sectional views of ananti-fuse structure formed in accordance with the present invention;

FIGS. 6-7 illustrate cross-sectional views of alternate anti-fusestructures in accordance with the present invention;

FIG. 8 is a flow diagram illustrating an overall process for forming ananti-fuse structure in the present invention; and

FIGS. 9a-9c are flow diagrams illustrating alternative processes forperforming step 56 in the process shown in FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 was discussed in terms of the prior art. FIGS. 2-7 presentstep-by-step cross-sectional views of the formation of an anti-fusestructure by the methods of the present invention. In FIG. 2, processedsubstrate 30 includes a semiconductor wafer 26 (such as a siliconwafer), a base oxide layer 28 formed over the semiconductor wafer 26, afirst metal layer 32 formed over the oxide layer 28, and an inter-metaloxide (IMO) layer 34 formed over the first metal layer 32. As describedto this point, the structure is substantially standard to the industry.

A strap layer 36 of TiW is formed over these layers. The TiW of strap 36is preferably sputter deposited to a thickness between about 1000 and10,000 angstroms (Å), with 2200 Å being a preferable thickness. The TiWlayer 36 is then patterned by standard photolithographic and etchtechniques to form the strap 36.

As used herein, the term "patterned" refers to photolithographic etchtechniques, whereby a resist material is applied to the upper surface ofthe layer being patterned, is exposed to a pattern of radiant energy,and is then developed to form a mask. An etching process is undertakento etch away the surface of the layer through the mask. At the end ofthe photolithography process, the mask is typically removed.

A layer 38 of anti-fuse material such as A-Si is then deposited andpatterned to remain only over the strap 36. Deposition is preferablyperformed by standard plasma enhanced chemical vapor deposition (PECVD)process. A range for the thickness of this layer 38 is between about500-5000 Å, with 1200 Å being a preferred thickness for 0.8 μmtechnologies.

FIG. 3 illustrates the structure of FIG. 2 with the addition of aninsulating layer 40. Silicon dioxide is a suitable material to use forthis insulating layer, and PECVD is the preferable deposition method. Anappropriate thickness for layer 40 is in the range of approximately1000-10,000 Å, with 3000 Å having been found to work well. A via 42 isformed by patterning layer 40 by standard photolithographic and etchtechniques. The lateral dimension "D" or width of the via is scalable toa desired dimension, but is preferably below about 0.8 μm, morepreferably below about 0.6 μm. Of course, the structure can also be usedwith vias having greater than 0.8 μm lateral dimensions, but isparticularly suitable for sub-micron applications.

In a first preferred embodiment of the present invention, as seen inFIG. 4, a conformal barrier layer 44 of a non-aluminum conductor isdeposited over the insulating layer 40 and into the via 42. Suitablenon-aluminum conductors include, for example, TiW and TiN(titanium-nitride). The thickness of this layer is preferably betweenabout 500-3000 Å, with 1000 Å having been found to work well. A suitabledeposition process for a TiN layer is chemical vapor deposition (CVD) orsputter deposition, while sputter deposition techniques are suitable forTiW. A plug layer 46 is then deposited as a blanket layer over thebarrier layer 44. Tungsten is preferably used as the plug layer 46, butW is not able to adhere well to the insulating oxide layer 40 so thatthe TiW or TiN also acts as an adhesion layer for the W plug deposition.The plug layer 46 is deposited to a thickness preferably approximately0.8 times the lateral dimension "D" of the via 42, where, in thisexample D is preferably about 0.8 μm.

FIG. 5 illustrates the structure of FIG. 4 following etch-back of theplug layer 46. This forms a W plug 47 in the via hole 42. By way ofexample, etch-back of the plug layer is performed by plasma etchtechniques well known to those skilled in the art. A layer 48 ofaluminum is then deposited over the plug 47. With the plug 47, theconductive layer 48 is kept well away from the A-Si layer 38, and thusthe possibility of degradation of the anti-fuse structure due todiffusion of the aluminum layer 48 into the antifuse layer 38 is all buteliminated.

The via hole 42 has a depth .(after the barrier layer 44 is provided)which extends from the top surface of the barrier layer 44 that iswithin the via hole 42 to the rim of the via hole 42 that has beenraised by the thickness of the barrier layer 44. As such, the depth ofthe via hole 42 is about the same depth of the via hole 42 before thebarrier layer 44 was deposited. Preferably, the plug 47 has a heightequal to at least one-half (1/2) of the depth of the via hole 42. Thisensures that any aluminum is kept well away from the anti-fuse layer andfurther ensures that the crucial corners of the via hole 42 are filledwith plug material.

Alternatives to the structure of FIG. 5 that maintain the separation ofthe aluminum layer from the anti-fuse layer are illustrated in FIGS. 6and 7. As shown in FIG. 6, the plug layer 46 is not etched-back from thevia opening 42. Rather, the entire layer 46 remains over the barrierlayer 44 and is also patterned as an interconnect. For low resistanceinterconnects, the conductive layer 48 is deposited over this blanketlayer 46, and the two layers are patterned together. This, again,separates the aluminum layer 48 from the A-Si layer 38.

Another alternative, as shown in FIG. 7, eliminates the layer 46. Thebarrier layer 44 when formed with TiN is capable of serving as a non-Alplug. TiN is suitable since it is deposited by CVD and is thereforecapable of filling the via 42. TiW, on the other hand, is deposited bysputter deposition and thus, would be unsuitable for filling the via 42.The TiN restricts the diffusion of the conductive layer 48 into theanti-fuse layer 38, while also acting as a suitable conductor duringprogramming of the anti-fuse structure. In this embodiment, a suitablethickness of the TiN is approximately 0.8 times the lateral dimension"D" of the via 42.

It is therefore a key element of the present invention to use a non-Alconductive plug in the via hole over an A-Si anti-fuse layer. By"non-Al" plug, it is meant that the great majority of the atoms of thematerial within the via are not free Al atoms that can react with theA-Si. For example, any Al atoms in the TiW or TiN should be less thanone part per million (ppm). Of course, it is impossible to provideabsolutely pure materials to form plugs within vias, but the essence ofthe present invention is to minimize, to the extent practical, thenumber of Al atoms within the via in proximity to the A-Si layer,thereby forming a substantially non-Al plug within the via.

It should also be noted that the term "non-Al plug" covers a variety ofstructures. In one embodiment, the "non-Al plug" is a conformal TiWbarrier layer with a "W plug" formed inside. In another embodiment, the"non-Al plug" is a conformal TiN barrier layer with a "W plug" formedinside. In a third embodiment, the "non-Al plug" is made from TiN.Therefore, the term "non-Al plug" will mean one or more conductivematerials deposited within a via, which singly or together substantiallyfill the via.

The flow diagram of FIG. 8 illustrates a process 49 in accordance withthe present invention. As shown, the process 49 begins with step 50 andthe deposition and patterning of a strap layer over an initialsubstrate. The substrate is preferably an IMO layer overlying a metallayer such as Al, which is formed on a prepared silicon wafer or thelike, as shown and described with reference to FIG. 2. TiW is suitablefor use as the strap layer. Standard photolithographic techniques arepreferably utilized to pattern the strap layer. At this stage of theprocess, the structure corresponds to layers 26-36 of FIG. 2.

Following the deposition and patterning of the strap layer, a layer ofanti-fuse material such as A-Si layer 38 is deposited, such as by PECVD,and patterned in step 52. A preferable range for the thickness of thislayer is between about 500-5000 Å, with 1200 Å being a suitablethickness for 0.8 μm technologies. Following the patterning step, thestructure appears as illustrated in FIG. 2.

After patterning of the anti-fuse layer 38 is completed, an insulatinglayer 40 is deposited in step 54. Silicon dioxide is appropriate forthis insulating layer. A via 42 is then etched through the insulatinglayer in the areas where the anti-fuse material is located. The via ispreferably established by plasma etching through the insulating layer bytechniques well known to those skilled in the art. The lateral dimensionof this via is preferably no greater than about 0.8 μm, with less than0.8 μm (e.g., 0.6 μm) being more preferable. At this point of theprocess, the structure appears as illustrated in FIG. 3.

The process 49 continues with step 56 and the deposition of a non-Alconductor barrier layer 44 over the insulating layer and into the via.It is at this point in the process that alternative procedures arepossible, as illustrated in the flow diagrams of FIGS. 9a-9c. As shownin FIG. 9a, in one embodiment, a process 56a involves three steps.First, in step 58, a barrier layer of a non-Al conductor is conformallydeposited over the insulating layer and into the via establishingcontact with the anti-fuse material. TiN, TiW, and other like materialsare usable for this step. The thickness of this layer is in the range ofabout 500-3000 Å, with 1000 Å having been found to work well. Next, aplug layer, suitably comprised of W, is deposited over the barrier layerin step 60. A suitable thickness of the plug layer is approximately 0.8times the lateral dimension D of the via 42. Then, in step 62, the pluglayer is etched-back to form a plug in the via hole. The structureresulting from this process is shown with reference to FIG. 5.

Alternatively, the flow diagram of FIG. 9b illustrates anotherembodiment, process 56b. This process is similar to that shown in FIG.9a, except that step 60, the etch-back step, is not performed in thismethod. Rather, the plug layer remains over the entire barrier layer andin the via. This arrangement is illustrated and described with referenceto FIG. 6.

A third alternative for process 56c is illustrated in FIG. 9c. Thisembodiment comprises only a single step 64 of depositing a barrier/pluglayer. For this embodiment, the barrier layer preferably comprises TiNsince the layer needs to be able to form a plug in the via hole, and TiNis suitably capable of being deposited as a plug by CVD. TiN, besidesbeing well-suited for plugformation by CVD deposition, also adheres wellto silicon dioxide (SiO₂) unlike W. TiW would not be a material assatisfactory for use as a plug due to the required use of sputterdeposition for its application, which could cause cusping, voids, andother defects. An appropriate thickness of the TiN for this embodimentis approximately 0.8 times the lateral dimension D of the via. Thestructure occurring with this embodiment is described in conjunctionwith FIG. 7.

The process then continues with the sequence illustrated in FIG. 8.Following step 56, (i.e., one of the processes 56a, 56b, or 56c) thenext step 66 is the deposition of a conductive layer, e.g., Al, over thenon-Al conductor layer. Alternatively, as the dashed arrow 66'indicates, since the barrier layer formed in step 56 is a conductivelayer, the Al layer can be eliminated in some instances, so that theprocess could end following step 56. In either case, the anti-fusestructure maintains a lower conductive layer, an anti-fuse layer, and atop conductive layer with a via plug of a non-Al material connecting thetop conductive layer with the bottom conductive layer through theanti-fuse layer. Accordingly, with this structure, anti-fuse programmingis accomplished by applying a programming voltage of approximately 10volts (V) between the conductive layers, and subsequent reading of theanti-fuse structure is accomplished by applying an appropriate sensingvoltage, as is well known to those skilled in the art.

Although only a few embodiments of the present invention have beendescribed in detail, it should be understood that the present inventionmay be embodied in many other specific forms without departing from thespirit or scope of the invention. Particularly, the invention has beendescribed in the context of a strap layer comprised of TiW.Alternatively, the TiW could be replaced with W. Further, the non-Alconductive barrier layer could be formed using chromium in addition toor instead of the TiN and TiW described. Further, the range ofthicknesses for the A-Si layer has been selected so that the layer isnot too thin which could lead to leaking or too thick which wouldrequire a high programming voltage. Of course, in alternate applicationshaving higher programming voltage capabilities, the upper limit on therange of thicknesses could be increased.

It is therefore intended that the following appended claims beinterpreted as including all such alterations, permutations, andequivalents as fall within the true spirit and scope of the presentinvention.

What is claimed is:
 1. An anti-fuse structure comprising:a conductivebase layer; a layer of anti-fuse material formed over said conductivebase layer; an insulating layer formed over said anti-fuse layer, saidinsulating layer being provided with a via hole to said anti-fuse layer,and said via hole .Iadd.having sides and .Iaddend.having a lateraldimension no greater than about 0.8 microns and having a depth; .Iadd.aconductive barrier layer consisting of a barrier material selected fromthe group consisting of TiW, TiN, and chromium said conductive barrierlayer having a first portion overlying said anti-fuse material a secondportion extending upward along said sides of said via hole and a thirdportion overlying a portion of said insulating layer; .Iaddend. aconductive non-Al plug .[.including a.]. .Iadd.above said first portionof said .Iaddend.conductive barrier .[.material chosen from the groupconsisting essentially of TiW, TiN, and chromium, provided within saidvia hole and in contact with said anti-fuse layer.]. .Iadd.layer.Iaddend.such that said anti-fuse structure may be programmed byproviding a programming voltage between said conductive base layer andsaid conductive barrier .[.material.]. .Iadd.layer.Iaddend., and may beread by providing a sensing voltage, which is lower than saidprogramming voltage, between said conductive base layer and saidconductive barrier material; and an electrically conductive layer formedover and in electrical contact with said plug, said electricallyconductive layer being separated from the anti-fuse layer by said plugby at least one-half said depth of the via hole.
 2. An anti-fusestructure as recited in claim 1 wherein said lateral dimension of saidvia hole is no greater than about 0.6 microns.
 3. An anti-fuse structureas recited in claim 1 wherein said conductive barrier .[.material.]..Iadd.layer .Iaddend.is conformably applied within said via hole, andwherein said non-Al plug further comprises a W plug within said via holeand in contact with said conductive barrier .[.material.]..Iadd.layer.Iaddend..
 4. An anti-fuse structure as recited in claim 3wherein said electrically conductive layer includes a conductive linecomprising aluminum over said conductive barrier .[.material.]..Iadd.layer .Iaddend.and in contact with said W plug.
 5. An anti-fusestructure as recited in claim 3 wherein said electrically conductivelayer and said W plug are integrally formed as parts of a blanket layerof tungsten over said conductive barrier .[.material.]. .Iadd.layer.Iaddend.and within said via hole.
 6. An anti-fuse structure as recitedin claim 5 wherein said tungsten blanket layer is patterned to provide atungsten interconnect contacting said plug.
 7. An anti-fuse structure asrecited in claim 3 wherein said electrically conductive layer comprisesa conductive line comprising aluminum over said insulating layer and incontact with said W plug.
 8. An anti-fuse structure as recited in claim1 wherein said .Iadd.conductive .Iaddend.barrier .[.material.]..Iadd.layer .Iaddend.comprises TiN which substantially completely fillssaid via hole as said non-Al plug.
 9. An anti-fuse structure as recitedin claim 1 wherein said conductive base layer has a thickness in therange of about 1000-10,000 Å.
 10. An anti-fuse structure as recited inclaim 9 wherein said conductive base layer has a thickness of about 2200Å.
 11. An anti-fuse structure as recited in claim 1 wherein saidanti-fuse material has a thickness in the range of about 500-5,000 Å.12. An anti-fuse structure as recited in claim 11 wherein said anti-fusematerial has a thickness of about 1200 Å.
 13. An anti-fuse structure asrecited in claim 1 wherein said insulating layer has a thickness in therange of about 1000-10,000 Å.
 14. An anti-fuse structure as recited inclaim 13 wherein said insulating layer has a thickness of about 3000 Å.15. An anti-fuse structure as recited in claim 1 wherein said conductivebarrier .[.material.]. .Iadd.layer .Iaddend.has a thickness in the rangeof about 500-3000 Å.
 16. An anti-fuse structure as recited in claim 15wherein said conductive barrier .[.material.]. .Iadd.layer .Iaddend.hasa thickness of about 1000 Å.
 17. An anti-fuse structure as recited inclaim 3 wherein said W plug has a height of at least 1/2 of said depthof said via hole.
 18. An anti-fuse structure as recited in claim 5wherein said blanket layer of tungsten has a thickness of about 0.8times the lateral dimension of the via hole.
 19. An anti-fuse structureas recited in claim 8 wherein said .Iadd.conductive .Iaddend.barrier.[.material.]. .Iadd.layer .Iaddend.has a thickness of about 0.8 timesthe lateral dimension of the via hole.
 20. An anti-fuse structure asrecited in claim 6 further comprising an aluminum interconnect providedover said tungsten interconnect.
 21. An anti-fuse structure as recitedin claim 5 wherein the plug substantially fills the via hole and whereinan aluminum layer is deposited over the blanket layer such that thealuminum layer is separated from the anti-fuse layer by at least aboutthe depth of the via hole.
 22. An anti-fuse structure as recited inclaim 21 wherein the electrically conductive layer has a thickness andwherein said distance separating the aluminum layer from the anti-fuselayer is equal to at least the height of the plug plus said thickness ofthe electrically conductive layer.